mask register मीनिंग इन हिंदी

उदाहरण वाक्य

1. A special register called the Mask Register held the base address.
2. An interrupt status register and interrupt mask register were provided in each of the four processor states.
3. Setting or clearing this mask may be faster than accessing an interrupt mask register ( IMR ) in a PIC or disabling interrupts in the device itself.
4. There are three registers, an Interrupt Mask Register ( IMR ), an Interrupt Request Register ( IRR ), and an In-Service Register ( ISR ).
5. The EVEX scheme is a 4-byte extension to the VEX scheme which supports the AVX-512 instruction set and allows addressing new 512-bit ZMM registers and new 64-bit operand mask registers.
6. The VFPCLASS instructions tests if the floating point value is one of eight special floating-point values, which of the eight values will trigger a bit in the output mask register is controlled by the immediate field.
7. A 32 bit " Priority Mask Register ", set by the " Change Priority Mask " instruction, could be used to selectively mask interrupts to keep them in pending status until the mask was reset.
8. The FP control unit had a hardware network for conditional microinstruction execution, with four mask registers and a condition-hold register; three bits in the microinstruction format select among nearly 50 conditions for determining execution, including result sign and overflow, I / O conditions, and loop control.